AD5541/ad5542 a rev. prd july 99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1999 +5v, serial input voltage output, 16-bit dacs preliminary technical data preliminary technical data features full 16-bit performance +5v single supply operation low power short settling time unbuffered voltage output capable of driving 60k w w w w w loads directly spi/qspi/microwire compatible interface standards power-on reset clears dac output to 0v (unipolar mode) schmitt trigger inputs for direct optocoupler interface applications digital gain and offset adjustment automatic test equipment data aquisition systems industrial process control general description the AD5541 and ad5542 are single 16 bit, serial input, voltage output dac's that operate from a single +2.7v to +5v supply. the AD5541 and ad5542 utilize a versatile three-wire interface that is compatible with spi tm , qspi tm and microwire tm interface standards. these dac's provide 16 bit performance without any adjustments. the dac output is unbuffered which reduces power consumption and offset errors contributed to by an output buffer. the ad5542 can be operated in bipolar mode generating a v ref output swing. the ad5542 also includes kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. the AD5541 and ad5542 are available in an so pack- age. functional block diagrams product highlights 1. single supply operation. the AD5541 and ad5542 are fully specified and guaranteed for a single +5v 5% supply. 2. low power comsumption. these parts consume typically 1.5mw with a +5 v supply 3. 3 wire serial interface. 4. unbuffered output capable of driving 60k w loads. this reduces power consumption as there is no internal buffer to drive. 5. power on reset circuitry. 16-bit dac 16-bit data latch serial input register control logic ref cs din sclk agnd v out v dd dgnd AD5541 16-bit dac 16-bit data latch serial input register control logic reff refs cs ldac din sclk agnds agndf v out inv rfb v dd dgnd r fb r inv ad5542 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
C2C rev. prd AD5541/ad5542Cspecifications (v dd = +5v 5%, v ref = +2.5v, agnd = dgnd = 0 v. all specifi- cations t a = t min to t max, unless otherwise noted.) preliminary technical data parameter min typ max units test conditions static performance resolution 16 bits relative accuracy 0.5 1.0 l s b l grade 0.5 2.0 l s b b, k grade 0.5 4.0 l s b a grade differential nonlinearity 0.5 1.0 l s b guaranteed monotonic gain error 5 lsb t a = +25c 10 l s b gain error temperature coefficient 0.1 ppm/c zero code error 1 lsb t a = +25c 2 lsb zero code temperature coefficient 0.05 ppm/c ad5542 bipolar resistor matching 1.0 r fb /r inv 0.015 % ratio error bipolar zero offset error 10 lsb t a = +25c 20 lsb bipolar zero temperature coefficient 0.5 ppm/c output characteristics output voltage range 0 v ref -1lsb v unipolar operation -v ref v ref -1lsb v ad5542 bipolar operation output voltage settling time 1 m s to 1/2lsb of fs, c l = 10pf slew rate 25 v/ m sc l = 10pf, measured from 0% to 63% digital-to-analog glitch impulse 10 nv-s 1 lsb change around the major carry digital feedthrough 10 nv-s dc output impedance 6.25 k w tolerance typically 20% power supply rejection ratio 1.0 lsb d v dd 10% dac reference input reference input range 2.0 v dd v reference input resistance 2 9k w unipolar operation 7.5 k w ad5542, bipolar operation logic inputs input current 1 m a v inl , input low voltage 0.8 v v inh , input high voltage 2.4 input capacitance 3 10 pf hysteresis voltage 3 0.4 v reference reference -3db bandwidth 1.3 mhz all 1s loaded reference feedthrough 1 mvp-p all 0s loaded, v ref = 1vp-p at 100khz signal-to-noise ratio 92 db reference input capacitance 75 p f code 0000 hex 120 p f code ffff hex power requirements v dd 4.75 5.25 v i dd 0.3 1.1 ma power dissipation 1.5 m w notes 1 temperature ranges are as follows: a, b versions: -40c to +85c, k, l versions: 0c to +70c. 2 reference input resistance is code dependent, minimum at 8555 hex. 3 guaranteed by design, not subject to production test. specifications subject to change without notice.
AD5541/ad5542 C3C rev. prd preliminary technical data preliminary technical data figure 1. timing diagram timing characteristics 1,2 parameter limit at t min , t max all versions units description f sclk 25 mhz max sclk cycle frequency t 1 40 ns min sclk cycle time t 2 20 ns min sclk high time t 3 20 ns min sclk low time t 4 15 ns min cs low to sclk high setup t 5 15 ns min cs high to sclk high setup t 6 35 ns min sclk high to cs low hold time t 7 20 ns min sclk high to cs high hold time t 8 15 ns min data setup tme t 9 0 ns min data hold time t 10 30 ns min ldac pulse width t 11 30 ns min cs high to ldac low setup t 12 30 ns min cs high time between active periods 1 guaranteed by design. not production tested. 2 sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are measured with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il +v ih )/2. specifications subject to change without notice. sclk t 2 t t 1 cs din db15 3 t 7 ldac* t 4 t 8 t 9 db0 t 5 t 6 t 10 t 11 *ad5542 only. may be tied permanently low if required. t 12 (v dd = +5v 5%, v ref = +2.5v, agnd = dgnd = 0 v. all specifications t a = t min to t max, unless otherwise noted.)
AD5541/ad5542 C4C rev. prd preliminary technical data preliminary technical data absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to agnd C0.3 v to +6 v digital input voltage to dgnd -0.3v to v dd +0.3 v v out to agnd -0.3v to v dd +0.3 v agnd, agndf, agnds to dgnd -0.3v to +0.3v input current to any pin except supplies 10ma operating temperature range industrial (a, b versions) C40c to +85c commercial (k, l versions) 0c to +70c storage temperature range C65c to +150c maximum junction temperature, (t j max) +150c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD5541/5542 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model relative accuracy temperature range package description package option AD5541lr 1 lsb 0c to +70c 8-lead small outline ic so-8 AD5541kr 2 lsb 0c to +70c 8-lead small outline ic so-8 AD5541br 2 lsb C40c to +85c 8-lead small outline ic so-8 AD5541ar 4 lsb C40c to +85c 8-lead small outline ic so-8 ad5542lr 1 lsb 0c to +70c 14-lead small outline ic so-14 ad5542kr 2 lsb 0c to +70c 14-lead small outline ic so-14 ad5542br 2 lsb C40c to +85c 14-lead small outline ic so-14 ad5542ar 4 lsb C40c to +85c 14-lead small outline ic so-14 package power dissipation (t j max C t a )/ q ja thermal impedance q ja soic(r-8) 149.5c/w soic(r-14) 104.5c/w lead temperature, soldering vapor phase (60 sec) +215c infrared (15 sec) +220c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD5541/ad5542 C5C rev. prd preliminary technical data preliminary technical data mnemonic pin description r f b 1 feedback resistor. in bipolar mode connect this pin to external op amp output. v out 2 analog output voltage from the dac. agndf 3 ground reference point for analog circuitry (force). agnds 4 ground reference point for analog circuitry (sense). refs 5 this is the voltage reference input (sense) for the dac. connect to external +2.5v refer ence. reference can range from 2v to v dd . reff 6 this is the voltage reference input (force) for the dac. connect to external +2.5v reference. reference can range from 2v to v dd . cs 7 this is a logic input signal. the chip select signal is used to frame the serial data input. sclk 8 clock input. data is clocked into the input register on the rising edge of sclk. duty cycle must be between 40% and 60%. n c 9 no connect. d i n 10 serial data input. this device accepts 16-bit words. data is clocked into the input register on the rising edge of sclk. ldac 11 ldac input. when this input is taken low, the dac register is simultaneously updated with the contents of the input register. dgnd 12 digital ground. ground reference for digital circuitry. inv 13 connected to the internal scaling resistors of the dac. connect inv pin to external opamps inverting input in bipolar mode. v dd 14 analog supply voltage, +5 v 5%. ad5542 pin function description AD5541 pin configuration ad5542 pin configuration 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v dd inv dgnd ldac agnds agndf rfb ad5542 din nc sclk cs reff refs nc = no connect top view (n ot t o s cale ) v out AD5541 pin function description mnemonic pin description v out 1 analog output voltage from the dac. agnd 2 ground reference point for analog circuitry. r e f 3 this is the voltage reference input for the dac. connect to external +2.5v reference. reference can range from 2v to v dd . cs 4 this is a logic input signal. the chip select signal is used to frame the serial data input. sclk 5 clock input. data is clocked into the input register on the rising edge of sclk. duty cycle must be between 40% and 60%. d i n 6 serial data input. this device accepts 16-bit words. data is clocked into the input register on the rising edge of sclk. dgnd 7 digital ground. ground reference for digital circuitry. v dd 8 analog supply voltage, +5 v 5%. soic soic din ref sclk cs 1 2 8 7 v dd dgnd agnd v out AD5541 3 4 6 5 top view (n ot t o s cale )
AD5541/ad5542 C6C rev. prd preliminary technical data preliminary technical data terminology relative accuracy for the dac's relative accuracy or endpoint linearity is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. gain error gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full- scale range. it is the deviation in slope of the dac trans- fer characteristic from ideal. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in ppm/c. zero code error zero code error is a measure of the output error when zero code is loaded to the dac register. zero code temperature coefficient this is a measure of the change in zero code error with a change in temperature. it is expressed in m v/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transi- tion. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. cs is held high, while the clk and din signals are toggled. it is specified in nv-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. power supply rejection ratio this specification indicates how the output of the dac is affected by changes in the power supply voltage. power- supply rejection ratio is quoted in terms of % change in output per % change in v dd for full scale output of the dac. v dd is varied by 10%. reference feedthrough this is a measure of the feedthrough from the v ref input to the dac output when the dac is loaded with all 0s. a 100khz, 1vp-p is applied to v ref . reference feedthrough is expressed in mvp-p.
AD5541/ad5542 C7C rev. prd preliminary technical data preliminary technical data general description the AD5541/5542 are single 16 bit, serial input, voltage output dacs. they operate from a single supply ranging from +2.7 v to +5 v and consume typically 300 m a with a supply of +5 v. data is written to these devices in a 16 bit word format, via a three or four wire serial interface. to ensure a known power up state, these parts were designed with a power on reset function. in unipolar mode the out- put is reset to 0v, while in bipolar mode, the ad5542 output is set to -v ref . kelvin sense connections for the reference and analog ground are included on the ad5542. digital-to-analog section the dac architecture consists of two matched dac sec- tions. a simplified circuit diagram is shown in figure 2. the dac architecture of the AD5541/5542 is segmented. the 4 msbs of the 16 bit data word are decoded to drive 15 switches e1 to e15. each of these switches connects one of 15 matched resistors to either agnd or v ref . the remaining 12 bits of the data word drive switches s0 to s11 of a 12 bit voltage mode r-2r ladder network. figure 2. dac architecture. in this type of dac configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependant. the output volt- age is dependant on the reference voltage as shown in the following equation. v out = v ref x d 2 n where d is the decimal data word loaded to the dac reg- ister and n is the resolution of the dac. for a reference of +2.5 v, the equation simplifies to the following. v out = 2.5 x d 65,536 giving a v out of 1.25 v with midscale loaded, and 2.5 v with full scale loaded to the dac. the lsb size is v ref /65,536. table 1. unipolar code table dac latch contents analog output msb lsb 1111 1111 1111 1111 v ref * (65,535/65,536) 1000 0000 0000 0000 v ref * (32,768/65,536) = 1/2v ref 0000 0000 0000 0001 v ref * (1/65,536) 0000 0000 0000 0000 0 v AD5541/ad5542 ad820/ dgnd * ad5542 only v dd refs* ref(reff*) out sclk din cs agnd_ 0.1 m f 0.1 +5v +2.5v external op amp unipolar output ldac* 10 m f m f op196 serial interface figure 3. unipolar output. unipolar output operation these dacs are capable of driving unbuffered loads of 60k w . unbuffered operation results in low supply current, typically 300 m a, and a low offset error. the AD5541 pro- vides a unipolar output swing ranging from 0 v to v ref . the ad5442 can be configured to output both unipolar and bipolar voltages. figure 3 shows a typical unipolar output voltage circuit. the code table for this mode of operation is shown in table 1. serial interface the AD5541 and ad5542 are controlled by a versatile 3-wire serial interface, which operates at clock rates up to 25 mhz and is compatible with spi, qspi, microwire and dsp interface standards. the timing diagram can be seen in figure 1. input data is framed by the chip select input, cs . after a high to low transition on cs , data is shifted synchronously and latched into the input register on the rising edge of the serial clock, sclk. data is loaded msb first in 16 bit words. after 16 data bits have been loaded into the serial input register, a low to high transition on cs transfers the contents of the shift register to the dac. data can only be loaded to the part while cs is low. the ad5542 has an ldac function which allows the dac latch to be updated asynchronously by bringing ldac low after cs goes high. ldac should be main- tained high while data is written to the shift register. al- ternatively, ldac may be tied permanently low to update the dac synchronously. with ldac tied permanently low, the rising edge of cs will load the data to the dac. 2r 2r r 2r r 2r 2r 2r s0 s11 e1 e2 e15 2r s1 vout v ref 4 msb's decoded into 15 equal segments 12 bit r-2r ladder
AD5541/ad5542 C8C rev. prd preliminary technical data preliminary technical data output amplifier selection for bipolar mode, a precision amplifier should be used, supplied from a dual power supply, this will provide the v ref output. in a single supply application, selection of a suitable opamp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case agnd. this can result in some degradation of the specified performance unless the application does not use codes near zero. the selected opamp needs to have very low offset voltage, (the dac lsb is 38 m v with a 2.5 v reference), to elimi- nate the need for output offset trims. input bias current should also be very low as the bias current multiplied by the dac output impedance (approx. 6k) will add to the zero code error. rail to rail input and output performance is required. for fast settling, the slew rate of the opamp should not impede the settling time of the dac. output impedance of the dac is constant and code independent, table 2. bipolar code table dac latch contents analog output msb lsb 1111 1111 1111 1111 +v ref * (32,767/32,768) 1000 0000 0000 0001 +v ref * (1/32,768) 1000 0000 0000 0000 0v 0111 1111 1111 1111 -v ref * (1/32,768) 0000 0000 0000 0000 -v ref * (32,768/32,768) = -v ref bipolar output operation with the aid of an external opamp, the ad5542 may be configured to provide a bipolar voltage output. a typical circuit of such operation is shown in figure 4. the matched bipolar offset resistors r fb and r inv are connected to an external opamp to achieve this bipolar output swing. table 2 shows the transfer function for this output operat- ing mode. also provided on the ad5542 are a set of kel- vin connections to the analog ground inputs. figure 4. bipolar output (ad5542 only). but in order to minimise gain errors, the input impedance of the output amplifier should be as high as possible. the amplifier should also have a 3db bandwidth of 1mhz or greater. the amplifier adds another time constant to the system, hence increasing the settling time of the output. a higher 3db amplifier bandwidth, results in a shorter effec- tive settling time of the combined dac and amplifier. force sense amplifier selection these amplifiers will be single supply, low noise amplifi- ers. a low output impedance at high frequencies is pre- ferred as they need to be able to handle dynamic currents of up to 20ma. reference and ground as the input impedance is code dependant, the reference pin should be driven from a low impedance source. the AD5541/5542 operates with a voltage reference ranging from +2 v to v dd . the dacs full scale output voltage is determined by the reference. tables 1 and 2 outline the analog output voltage for particular digital codes. for optimum performance, kelvin sense connections are pro- vided on the ad5542. if the application doesnt require separate force and sense lines, they should be tied together close to the package to minimize voltage drops between the package leads and the internal die. power on reset these parts have a power on reset function to ensure the output is at a known state upon power up. on power up, the dac register contains all zeros, until data is loaded from the serial register. however, the serial register is not cleared on power up, so its contents are undefined. when loading data initially to the dac, 16 bits or more should be loaded to prevent erroneous data appearing on the out- put. if more than 16 bits are loaded, then the last 16 are kept, and if less than 16 are loaded, then bits will remain from the previous word. if the AD5541/5542 needs to be interfaced with data shorter than 16 bits, then the data should be padded with zeros at the lsbs. power supply and reference bypassing for accurate high resolution performance, it is recom- mended that the reference and supply pins be bypassed with a 10 m f tantalum capacitor in parallel with a 0.1 m f ceramic capacitor. ad5542 dgnd v dd refs reff out sclk din cs agnds 0.1 m f 0.1 +5v +2.5v external op amp bipolar output ldac 10 m f m f serial interface agndf r inv r fb rfb inv +5v -5v
AD5541/ad5542 C9C rev. prd preliminary technical data preliminary technical data 8-lead so (so-8) 14 lead so (r-14) 0.1968 (5.00) 0.1890 (4.80) 85 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 o 0 o 0.0196 (0.50) 0.0099 (0.25) x 45 o outline dimensions dimensions shown in inches and (mm).
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